Pushkar Ranade, Chris Auth, Jack Kavalieros: What will computer chips look like in 2045?

The framing is a supply shock rather than a technology story. AI demand is, by one Intel executive's estimate, easily forty to fifty percent above maximum capacity — a gap the industry has not seen before. That number is the reason the rest of the episode is about factories rather than models.

The chain runs from exponentially increasing compute, to foundries that must build far more leading-edge capacity and make each chip do more, to the tools those foundries buy from suppliers — most famously ASML's EUV machines. Without the equipment, the chips cannot be made at all. Dwarkesh spent two days touring Intel's fabs to make that chain concrete, and the interviews that follow are with the people who run it.

Chris Auth leads development of all processes currently in manufacturing, and the question put to him is deliberately operational: if 14A ships in two or three years, what happens between now and then? His answer is that three-plus years of pre-work are already done and the process is close to being finalised — the tool sets are being fixed and each of roughly two thousand process steps is being fine-tuned so that it can run thousands of wafers a week, repeatably.

Yield improvement is the visible metric, and it is driven by two defect-detection channels: inline metrology that inspects wafers as they move through the line, and end-of-line electrical test or sort that locates failures. A cross-section of a failing site, taken in the TEM lab, identifies which layer the defect sits between, which in turn identifies the section of the flow responsible — and that section's inline data says which defects to chase. The strategic lesson Auth draws from this is about pacing: too much innovation in one node makes the process too complex to land on the schedule the customer wants, so the question is always how much innovation can be afforded within the timeline.

That tradeoff has a price tag in Intel's own history. The 10nm node was targeted for 2016 and did not begin manufacturing until 2018; Intel, historically the keeper of a two-year cadence, slipped almost four years, and the market reaction was severe — Intel's worst day in four months, down more than fifteen percent, with TSMC up thirteen percent on the news.

Auth's account is that 10nm pursued aggressive targets through what was then called hyperscaling, inventing ways to scale faster than had been done before without new tools, because the tools were not ready — which loaded the process and the engineers with burden. The technology eventually reached world-class yield, performance and cost, but later than wanted. Asked what should have been deferred, he names EUV: when 10nm was being defined, the conclusion was that EUV was not ready.

The cost of that judgement is measured in experience. EUV prints with 13.5-nanometer light, about fourteen times shorter than the previous generation, and shorter wavelength means finer features per exposure. TSMC put EUV into volume manufacturing in 2019 and extended it on 5nm in 2020; Intel's first EUV process did not reach products until 2023, leaving TSMC roughly four more years with the machines.

The institutional response to 10nm was a set of maturity metrics administered through a phase gate: to move a technology from pathfinding into development, it must clear yield, defect and performance criteria, and anything that fails is pushed to a later node. Only what is ready gets run, because staying on schedule is the binding constraint. The gate is the mechanism by which the abstract lesson — limit innovation per node — becomes an actual decision.

Schedule pressure collides with a physics-and-materials timeline that no amount of urgency compresses. The modern transistor descends from the planar MOS device demonstrated in 1960, and its history is a progression from two dimensions into three. A transistor is a switch: a gate on top of silicon between source and drain, a positive voltage pulling electrons up to form a conducting channel beneath a thin insulator, and the voltage removed to switch off. As devices shrank, source and drain came close enough that current leaked through the channel even when off, and the fix was to give the gate a tighter grip by touching the channel on more sides.